The present invention relates to a logic simulation system, and more particularly to a hardware logic simulation accelerator.
One of the most difficult problems associated with hardware logic simulation accelerators is the modeling of devices. In a software simulator, there is almost unlimited flexibility in determining device operation. In a hardware accelerator, the operation of the simulated device is constrained by the capabilities designed into the hardware of the evaluator.
Existing hardware accelerators allow devices to be modeled in either a "pulse pass" (delay line mode) or in a "pulse suppress" (filter mode). In the pulse pass mode, the rising and falling output delays must be equal. In the pulse suppress mode, the rising and falling delays may be different. However, there is a need for an additional delay mode.
There are two facts which lead to the need for an additional delay mode. These two facts are: (1) Most actual logic circuit processes result in different rising and falling delays (this is especially true for the CMOS process); (2) It is desirable to know that the inputs to a device changed in such a way as to cause an output change even if the duration of the input state was less than the device propagation delay. The pulse pass mode does not allow the different rising and falling delays to be modeled, and the pulse suppress mode hides the input changes which do not exist for a period of time sufficient to pass the pulse. A pulse amplify mode would allow the rising and falling propagation delays to differ without sacrificing the ability to detect input changes with duration less than the device propagation delays.
An additional benefit which is gained by supporting a pulse amplify mode is that parameter checking is simplified for complex cell design. For example, it is desirable in flip flop models to detect violations of setup time, hold time, clock pulse width, etc. This detection can be done by using pulse amplify mode in certain primitives within the flip flop cell.